Allwinner A20 processor is a dual-core ARM Cortex-A7 mobile application solution designed for tablet and smart TV applications.
A20 processor is based on a dual-core ARM Cortex-A7 CPU architecture, which is the most energy efficient application processor from ARM so far and incorporates all the features of Cortex-A15. It also integrates the powerful ARM Mali400 MP2 GPU, delivering a reliable system performance as well as good game compatibility. Besides,A20 supports 2160p video decoding and H.264 HP 1080p video encoding.
Additionally, A20 processor features a wide range of interfaces and connectivity, including 4-CH CVBS in, 4-CH CVBS out, HDMI with HDCP, VGA, LVDS/RGB LCD, SATA, USB, and GMAC, etc. More importantly, A20 processor is pin-compatible with its predecessor A10, which greatly simplifies the product design process and makes the upgrade of a design much easier.
Product Information
Name: A20+AXP209 chipset
Property： Software open source, Hardware open
Owner: Allwinner Technology
Demoboard: http://www.cubietech.com/product-detail/cubieboard2/
http://www.cubietech.com/product-detail/cubieboard3/
http://www.cubietech.com/product-detail/cubieaio-a20-board/
Target: Manufacturer
Product Features
Dual-Core CPU
● Dual Cortex-A7
–ARMv7 ISA standard ARM instruction set
–Thumb-2
–Jazeller RCT
–NEON Advanced SIMD
–VFPv4 floating point
–Hardware virtualization support
–Large Physical Address Extensions(LPAE)
–JTAG debug
–One general timer for individual CPU
–32KB Instruction and 32KB Data L1 Cache for individual CPU
Graphic Engine
● 3D
–Mali400 MP2 GPU
–Support OpenGL ES 2.0 / OpenVG 1.1 standard
● 2D
–Support BLT and ROP2/3/4
–Support 90° /180° /270° rotation
–Support mirror/ alpha (plane and pixel alpha) /color key
–Format conversion: ARGB 8888/4444/1555,RGB565, MONO 1/2/4/8bpp, Palette 1/2/4/8bpp(input only), YUV 444/422/420
Memory
● Internal BROM
–Support system boot from NAND Flash, SPI Nor Flash (SPI0), SD Card/TF card (SDC0/2)
–Support system code download through USB OTG (USB0)
● SDRAM
–Support DDR3/DDR3L/DDR2
–Support 32-bit bus width
–Support 2GB address space
● NAND Flash
–Comply to ONFI 2.3 and Toggle 1.0
–Support 64 bits ECC per 512 bytes or 1024 bytes
–Support 8bits data bus width
–Support 1.8V/3.3V signal voltage
–Support 1K/2K/4K/8K/16K page size
–Support up to 8 CE and 2 RB
–Support system boot from NAND flash
–Support SLC/MLC NAND and EF-NAND
–Support SDR/DDR NAND interface
● SD/MMC Interface
–Comply with eMMC standard specification V4.3
–Comply with SD physical layer specification V3.0
–Comply with SDIO card specification V2.0
–Support 1/4/8 bits bus width
–Support HS/DS/SDR12/SDR25 bus mode
–Support eMMC mandatory and alternative boot operations
–Support four independent SD/MMC/SDIO controllers
–Support SDSC/SDHC/SDXC/MMC/ RS-MMC card
–Support eMMC/iNand Flash
–Support 1GB/2GB/4GB/8GB/16GB/32GB/64GB/128GB SD/MMC card
–Support SDIO interrupt detection
–Support descriptor-based internal DMA controller for efficient scatter and gather operations
System Resources
● Timer
–6 timers: clock source can be switched over 24M/32K for all timers, and external signals can be used as clock source for Timer4/5
–Two 33-bit AVS counters
–Watchdog to generate reset signal or interrupt
–Real time counter for second, minute, hour, day, month, and year
● High Speed Timer
–4 channels
–Clock source is fixed to AHB, and the pre-scale ranges from 1 to 16
–56-bit counter that can be separated to 24-bit high register and 32-bit low register
● DMA
–16 channels
–Support data width of 8/32 bits
–Support linear and IO address modes
● CCU
–8PLLs, a main 24MHz oscillator, an on-chip RC oscillator and a 32768Hz oscillator (optional)
● GIC
–Support 16 SGIs, 16 PPIs, and 128 SPIs
–Support ARM architecture security extensions
–Support ARM architecture virtualization extensions
–Support uniprocessor and multiprocessor environments
Video Engine (Phoenix 3.0)
● Video Decoding
–Support picture size up to 3840×2160
–Support decoding speed up to 1080p@60fps
–Supported formats: Mpeg1/2, Mpeg4 SP/ASP GMC, H.263 including Sorenson Spark, H.264 BP/ MP/HP, VP6/8, AVS jizun, Jpeg/Mjpeg, etc.
● Video Encoding
–H.264 HP up to 1080p@30fps
–Jpeg baseline: picture size up to 4080×4080
–Alpha blending
–Thumb generation
–4×2 scaling ratio from 1/16 to 64 arbitrary non-integer ratio
Display Engine
● Four moveable and size-adjustable layers, each layer size up to 8192×8192 pixels
● Ultra-Scaling engine
–8-tap scale filter in horizontal and 4 tap in vertical
–Source image size from 8×4 to 8192×8192 resolution and destination image size from 8×4 to 8192×8192 resolution
● Support multiple image input formats
–mono 1/2/4/8 bpp
–palette 1/2/4/8 bpp
–6/24/32 bpp color
–YUV444/420/422/411
● Support alpha blending/color key/gamma/harware cursor/sprite
● Output color correction: luminance/hue/saturation, etc
● Support de-interlace
● Video enhancement: lum peaking/DCTi/black and white level extension
● 3D input/output format conversion and display
Video Output
● HDMI 1.4 transmitter with HDCP
● LVDS/Sync RGB/CPU LCD interface up to 1920×1200 resolution
● Support 4-channel CVBS, or 2-channel S-video, or 1-channel YPbPr/VGA (YPbPr/VGA up to 1080p)
● Support two-channel independent display
Video Input
● Support TV decoder: 4-ch analog CVBS or 1-ch YPbPr(480i/576i/480p/576p) signal input
● Dual CMOS sensor parallel interfaces that support YUV format only
–CSI0 up to 1080p@30fps
–CSI1 up to 720p@30fps
● Support BT656 interface
● Support 24-bit YUV444/RGB interface
Analog Audio Output
● Stereo audio DAC
● Stereo capless headphone drivers
–Up to 100dB SNR during DAC playback
–Support 8KHz~192KHz DAC sample rate
● One low-noise analog microphone bias
● Dedicated headphone outputs
● Two mixers to meet different requirements
–Output mixer for LINEINL/R, FMINL/R, MIC1/2 and Stereo DAC output
–ADC record mixer for LINEINL/R, FMINL/R, MIC1/2 and Stereo DAC output
Analog Audio Input
● Support four analog audio inputs
–Two microphone inputs
–Differential or stereo line-in input
–Stereo FM-in input
● Stereo audio ADC
–96dBA SNR
–Support 8KHz ~ 48KHz ADC sample rate
RTP
● 12-bit SAR ADC
● Dual touch detection
● Sampling frequency up to 2MHz
Connectivity
● USB2.0 OTG
–Support High-Speed (HS, 480-Mbps), Full-Speed (FS, 12-Mbps), and Low-Speed (LS, 1.5-Mbps) in Host mode
–Support High-Speed (HS, 480-Mbps), Full-Speed (FS, 12-Mbps) in Device mode
–Support up to 5 user-configurable endpoints for Bulk , Isochronous, Control and Interrupt
● USB EHCI/OHCI
–Two EHCI/OHCI-compliant hosts
● EMAC
–Support 10/100Mbps MII data transfer rate
● GMAC
–Comply with the IEEE 802.3-2002 standard
–Programmable frame length to support Standard or Jumbo Ethernet frames with size up to 16KB
–Support 10/100/1000Mbps data transfer rates RGMII interface to communicate with an external Gigabit PHY
–Support 10/100Mbps MII PHY interface
● Digital Audio In/Out
–One I2S compliant audio interface, supporting 8-channel and 2-channel input
–One PCM, supporting linear sample(8-bit or 16-bit), 8-bit u-law and A-law companded sample
–One AC97 audio codec, supporting 2-channel and
6-channel audio data output
● Transport Stream Controller
–Support both SPI and SSI
–Speed up to 150Mbps for both SPI and SSI
–Support 32-channel PID filter
–Support hardware PCR packet detect
● Open-Drain TWI
–Up to 5 TWIs compliant with TWI protocol
● Smart Card Reader
–One smart card reader controller supporting ISO/IEC 7816-3 and EMV2000 specifications
–Support synchronous and any other non-ISO 7816 and non-EMV cards
● SPI
–Master/Slave configurable
–Up to 4 independent SPI controllers: SPI0 with one CS signal for system boot, SPI1/2/3 each with two CS signals
● UART
–Up to 8 UART controllers:UART0 with two wires for debug tools, UART1 with 8 wires, UART2/3 each with 4 wires, and others each with 2 wires
● PS2
–Two PS2 compliant to IBM PS2 and AT-compatible keyboard and mouse interface
–Dual-role controller: a PS2 host or a PS2 device
● IR
–Two IR controllers supporting CIR, MIR and FIR modes
● SATA
–One SATA Host controller
–Support SATA 1.5Gb/s and SATA 3.0Gb/s
–Comply with SATA spec 2.6
–Support external SATA(eSATA)
● CAN
–One CAN bus controller
–Support the CAN2.0 A/B protocol specification
–Programmable data rate up to 1Mbps
● Keypad
–One keypad matrix interface up to 8 rows and 8 colums
–Interrupt for key press or key release
–Internal debouncing filter to prevent switching noises
● LRADC
–6-bit resolution
–Voltage input range between 0V to 2V
● PWM
–2 PWM outputs
–Support cycle mode and pulse mode
–The pre-scale is from 1 to 64
Security System
● Security System
–Support AES, DES, 3DES, SHA-1, MD5
–Support ECB/CBC/CNT modes for AES/
DES/3DES
–128-bit, 192-bit and 256-bit key size for AES
–160-bit hardware PRNG with 192-bit seed
● Security JTAG
Power Management
● Flexible PLL clock generator and OSC for 32KHz
● Flexible clock gate
● Support DVFS for CPU frequency and voltage ad-justment
● Support standby mode (only DDR+RTC-Domain power exist)
Package
● FBGA 441 balls,0.80mm ball pitch, 19x19x1.4mm
Other Specifications
Operating Temperature: -20℃~70℃
Environment Friendly: RoHS
Packing Weight: Packing Size:
Development Materials
Technical Website: http://cubieboard.org/
Resources and Materials: http://dl.cubieboard.org/model/CubieBoard2/
Distribution contacts: sales@cubietech.com
Technical contacts: support@cubietech.com
Distributor: sales@cubietech.com
